The present invention relates to a microcomputer including a plurality of pipeline stages for executing a plurality o f sequentially given instructions in synchronism with an operation clock.
A microcomputer, provided with a plurality of pipeline stages, including an instruction fetch stage (IF stage), an instruction decoding stage (DEC stage) and an instruction execution stage, is well known. The central processing unit (CPU) of such a microcomputer includes: an instruction fetch circuit for fetching an instruction; an instruction decoding circuit for decoding the fetched instruction; an instruction execution circuit for executing the decoded instruction; and a pipeline control circuit for controlling the pipeline processing performed by the instruction fetch circuit, the instruction decoding circuit and the instruction execution circuit. The instruction execution circuit is provided with a plurality of stages including, for example: an operation execution stage (EX stage) for performing operand address operations and/or operations on the operands read out from a resister set; a memory access stage (MEM stage) for accessing a data memory; and a write back stage (WB stage) for writing data words representing the operation results and/or the data words provided from the data memory into the register set. The MEM stage is sometimes subdivided into a plurality of sub-stages (e.g., MEM1 and MEM2 stages).
A data cache is often intervened between the instruction execution circuit and the data memory. If a clock rate is high, not only the CPU but also the data cache should have a pipeline structure. However, it is the user of a microcomputer that determines the frequency of the operation clock to be supplied to the microcomputer. Thus, even a microcomputer having such a configuration as ensuring high performance at a high clock rate would not always guarantee high performance at a low clock rate so long as the configuration lacks in flexibility.